-------------------------------------------------------------------------------
--
-- Title       : No Title
-- Design      : 
-- Author      : aldec
-- Company     : Microsoft
--
-------------------------------------------------------------------------------
--
-- File        : c:\Users\vincenti\Desktop\testworkspace\wkspace\test3\src\test_TB\test_tb3.vhd
-- Generated   : 02/10/15 16:11:39
-- From        : c:\Users\vincenti\Desktop\testworkspace\wkspace\test3\src\test.asf
-- By          : ASFTEST ver. v.2.1.3 build 56, August 25, 2005
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;


library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;

entity test_ent_tb3 is
end entity test_ent_tb3;

architecture test_arch_tb3 of test_ent_tb3 is
  constant delay_wr_in : Time := 5 ns;
  constant delay_pos_edge : Time := 5 ns;
  constant delay_wr_out : Time := 5 ns;
  constant delay_neg_edge : Time := 5 ns;

  file RESULTS : Text open WRITE_MODE is "results.txt";

  procedure WRITE_RESULTS(
    constant  CLK : in Std_logic;
    constant  a : in Std_logic;
    constant  reset : in Std_logic;
    constant  clk_en : in Std_logic;
    constant  z : in Std_logic
 ) is
     variable l_out : Line;
  begin
     WRITE(l_out, now, right, 15, ps);
     -- write input signals
     WRITE(l_out, CLK, right, 8);
     WRITE(l_out, a, right, 8);
     WRITE(l_out, reset, right, 8);
     WRITE(l_out, clk_en, right, 8);
     -- write output signals
     WRITE(l_out, z, right, 8);
     WRITELINE(RESULTS, l_out);
  end;

  component test is
    port(
      CLK : in Std_logic;
      a : in Std_logic;
      reset : in Std_logic;
      clk_en : in Std_logic;
      z :out Std_logic);
  end component; -- test;

 signal CLK : Std_logic;
 signal a : Std_logic;
 signal reset : Std_logic;
 signal clk_en : Std_logic;
 signal z : Std_logic;

 signal cycle_num : Integer; -- takt number

-- this signal is added for compare test simulation results only
type test_Sreg0_type is (S1, S3, S2, any_state);
signal  test_Sreg0 : test_Sreg0_type;


begin
   UUT : test
   port map(
    CLK => CLK,
    a => a,
    reset => reset,
    clk_en => clk_en,
    z => z);

 STIMULI : process
 begin
 --  Test reset - state(i)

   CLK <= '0';   
   cycle_num <= 0;           
   wait for delay_wr_in;
   a <= '0';
   reset <= '1';
   clk_en <= '0';

   wait for delay_pos_edge;
   test_Sreg0 <= S1;
   CLK <= '1';
   wait for delay_wr_out;
   wait for delay_neg_edge; -- S1

   CLK <= '0';   
   cycle_num <= 1;           
   wait for delay_wr_in;
   a <= '1';
   reset <= '0';
   clk_en <= '1';

   wait for delay_pos_edge;
   test_Sreg0 <= S2;
   CLK <= '1';
   wait for delay_wr_out;
   wait for delay_neg_edge; -- S2

   CLK <= '0';   
   cycle_num <= 2;           
   wait for delay_wr_in;
   a <= '1';
   reset <= '0';
   clk_en <= '1';

   wait for delay_pos_edge;
   test_Sreg0 <= S3;
   CLK <= '1';
   wait for delay_wr_out;
   wait for delay_neg_edge; -- S3

   CLK <= '0';   
   cycle_num <= 3;           
   wait for delay_wr_in;
   reset <= '1';

   wait for delay_pos_edge;
   test_Sreg0 <= S1;
   CLK <= '1';
   wait for delay_wr_out;
   wait for delay_neg_edge; -- S1

   CLK <= '0';   
   cycle_num <= 4;           
   wait for delay_wr_in;
   a <= '1';
   reset <= '0';
   clk_en <= '1';

   wait for delay_pos_edge;
   test_Sreg0 <= S2;
   CLK <= '1';
   wait for delay_wr_out;
   wait for delay_neg_edge; -- S2

   CLK <= '0';   
   cycle_num <= 5;           
   wait for delay_wr_in;
   reset <= '1';

   wait for delay_pos_edge;
   test_Sreg0 <= S1;
   CLK <= '1';
   wait for delay_wr_out;
   wait for delay_neg_edge; -- S1


 -- Test length 6
  wait;      -- stop simulation
 end process; -- STIMULI;

 WRITE_RESULTS(CLK,a,reset,clk_en,z);

end architecture test_arch_tb3;

configuration test_cfg_tb3 of test_ent_tb3 is
   for test_arch_tb3
      for UUT : test  use entity work.test(test_arch);
      end for;
   end for;
end test_cfg_tb3;
